MLG - Mask Layout Generator
- Main features
- - Automatic main chip, dropin chip, frame cell, test line placement and protection block generation
- - Single chip and multiple chips (MPW) handling
- - Drop-in test key (test module) handling
- - Multi-Fields handling
- - Visual & friendly GUI floor plan editing
- - Customized placement rule file
- - Placement Rule Check (PRC)
- - Optimized wafer layout generation and gross die calculation
- - Mask floor plan report generation
- - Single chip and multiple chips (MPW) handling
MLG is a tool for mask layout generation. It is designed for generating of mask floor plan easily and automatically.